Automatic Testing of Microprocessor in Radiation Environments Journal of Test Engineering 2nd issue by Ronald C. Alexander

Describing work performed in 1982-3 at Harry Diamond Laboratories, Adelphi, MD 20783


Abstract


A system for the acquisition of real-time failure data has been designed for in-situ total 
ionizing dose testing of large-scale integrated circuits. System selection consideration and 
analysis features are described using the Intel MCS-51 micro-controller family as an example.

Introduction


Testing any piece-part for ionizing radiation hardness requires an approach which ensures that 
the part will be exercised in a manner and environment that adequately characterize the dose 
at which the device would fail in its application. To provide meaningful failure data to 
developers of military systems, we exercise and monitor the device under test (DUT) while it 
is being irradiated. This avoids the errors introduced by annealing of the radiation damage 
in the time it would take to transport the DUT to a test machine. One problem which arrises 
in the evaluation of microprocessors, however, is the design of a program efficient enough 
to exercise the DUT thoroughly in a short period of time (<5 s). The shorter the time, the 
better precision one has on the failure dose.

A microprocessor can be characterized by the voltages at a set of its electrical connection 
pins at specific observation times. This collection of voltages is called a state vector of 
the device at the specified observation time. In testing the MCS-51 microcontroller we have 
chosen a state vector consisting of the address (11 lines) and data (8 lines) and the program 
store enable strobe line. This state vector is sampled at a peripheral firmware storage chip. 
Choice of the peripheral chip as the sampling site rather than the DUT is dictated by our need 
for the in-situ radiation testing. The state vector is observed once during each of the DUT's 
memory access cycles. The MCS-51 memory access cycle is six oscillator periods, and our test 
is run with a 12-MHz oscillator. By gather ing this type of data, we may be able to identify 
the area of the processor which fails.

Logic Analyzer Subsystem


The Nicolett-Parasonics NPC-764 logic state analyzer (LSA) was chosen for data acquisition 
because of its unique programmability. It is designed around an IEEE-488 bus over which data 
can be stored on mass storage (Figure 1). Test sequencing can be programmed on its integrated 
microcomputer system. Commands may be sent over the IEEE-488 bus in ASCII mnemonic via the 
microcomputer's bus controller. The microcomputer operating system is CP/M, and the bus 
controller firmware is included in the system's input/output read-only memory. Our test 
software is written in assembly language to facilitate efficient access to the IEEE-488 bus, 
and a library of IEEE-488 bus process drivers was developed to facilitate test program design. 
Each process driver module may be included in any test sequencing program and called as a 
subroutine.

The LSA can be thought of as a peripheral of of the integrated imcrocomputer. Communication 
with peripherals, including the LSA, is straightforward using the process drivers (Figure 2). 
An RS-2332 port is available on the NPC-764, and data transmission over the RD232, as well 
as receipt of external control signals, may be included in the test sequence program via 
instructions to the LSA.

Data Collection


Data are collected in sets if 1000 state vectors by the LSA. The acquisition of each set is 
triggered by the appearance of a reset state vector at the collection site. The NPC-764 
provides a derived signature unique to distinct data sets. When the signature of a current set 
is compared with the preirradiated signature, a single bit error can be identified in any one 
of the 1000 state vecotrs. After any failure, the test sequence program will cause the NPC-764 
data set to be saved on flexible disk over the IEEE-488 bus.

The current state of the NPC-764 is saved with the data set. Under test sequence program 
control, the researcher may select to resume control, the researcher may select to resume 
testing of the DUT with the fail data set as reference. For example, they may elect to 
alternate between the original data set and the fail data set. This allows the researcher 
to observe device recovery behavior.

A state vector must be chosen for each new device to be tested. A problem arises because 
internal buses cannot be accessed in most microprocessors and microcomputers. The design 
of firmware to cause internal registers to be transferred via the accumulator to the 
external bus, or the choice of a clock to trigger the acquisition of the state vector 
may multiply the information available in the data sets.

Radiation Hardness Testing


We hope that recording enough data under various environmental and recovery state conditions 
will allow the researcher to focus in on the weakest area of the chip. This could point the 
chip manufacturer toward possible design changes. Before the introduction of automatic test 
software into the device test field, the typical hardness test consisted of recording the 
dose level at which functional failure occured. Recovery times were only sometimes recorded. 
This type of failure data was not indicative of specific internal failure areas. However, 
it indicated only the relative merit of various processing approaches, as represented by the 
various products and manufacturers. The data were used at the system design level to slect 
device families or manufacturers whose parts would ensure survivability.

The advent of automatic testing allows the researcher to expand the type and amount of data 
to be gathered. We may include tests of specific internal device capabilities. In testing 
microcontrollers we may observe that failure occurs during a specific command subset. The 
integrated circuit designer could use these data to modify their design rules to achieve 
better hardness using the same process line.

The characterization of a device as radiation hardened is only of concern to a limited market 
sector. Since there has been only small demand for hardened parts, there has been little 
economic incentive for manufacturers to change process lines to increase hardness. Design 
rule modifications suggested by expanded test data may allow changes in design to be made at 
the reticle rather than process line, achieving increased hardness with significantly less 
cost. The increasing use of data acquisition techniques to identify design changes which 
increase reliability or survivability with a minimum of cost impact is clearly desirable.

About the Author, Ronald C. Alexander


Mr. Alexander received his BS in Mathematics from the University of the State of New York in 
1978 and his BS in Electrical Engineering from the University of Portland in 1979. From 1973 
to 1977, he served on submarines in the Atlantic. During 1979, while at Bonneville Power 
Administration (BPA), he developed a Nuclear Power Plant Utilization Simulator for use on the 
BPA's CDC Computer. Since beginning with the Department of Defense in 1980, he has developed 
numerous automatic test procedures using Hewlett-Packard ATS-1000 test systems at Naval 
Undersea Warfare Engineering Station (NUWES), Keyport, WA, and in 1981 developed the NUWES 
ATS-1000 Users Course. Since 1982, Mr. Alexander has been working in the Large-Scale 
Integrated Device Evaluation Group of the Transient Radiation Effects and System Generated 
Electromagnetic Pulse Branch at Harry Diamond Laboratories, Adelphi, MD.

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